This relates generally to integrated circuit packages, and more particularly, to integrated circuit packages with more than one integrated circuit die. An integrated circuit package typically includes an integrated circuit die and a substrate on which the die is mounted. The die is often coupled to the substrate through bonding wires or solder bumps. Signals from the integrated circuit die may then travel through the bonding wires or solder bumps to the substrate.
As demands on integrated circuit technology continue to outstrip even the gains afforded by ever decreasing device dimensions, more and more applications demand a packaged solution with more integration than possible in one silicon die. In an effort to meet this need, more than one die may be placed within a single integrated circuit package (i.e., a multichip package). As different types of devices cater to different types of applications, more dies may be required in some systems to meet the requirements of high performance applications. Accordingly, to obtain better performance and higher density, an integrated circuit package may include multiple dies arranged laterally along the same plane or may include multiple dies stacked on top of one another.
The multiple dies within a multichip package communicate with one another through inter-die package traces or other conductive paths formed in the package. These package interconnects often exhibit low yield due to manufacturing defects, which reduces the final assembly yield of the package. Several schemes for increasing the final assembly yield have been proposed but they all require use of complex encoding circuits (which takes up valuable die area) and can consume an excessive amount of power (which pushes down circuit performance).
It is within this context that the embodiments described herein arise.